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<title>VFNMADD132SD/VFNMADD213SD/VFNMADD231SD—Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values </title></head>
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<h1>VFNMADD132SD/VFNMADD213SD/VFNMADD231SD—Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op /En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>VEX.DDS.LIG.66.0F38.W1 9D /r</p>
<p>VFNMADD132SD xmm1, xmm2, xmm3/m64</p></td>
<td>RVM</td>
<td>V/V</td>
<td>FMA</td>
<td>Multiply scalar double-precision floating-point value from xmm1 and xmm3/mem, negate the multiplication result and add to xmm2 and put result in xmm1.</td></tr>
<tr>
<td>
<p>VEX.DDS.LIG.66.0F38.W1 AD /r</p>
<p>VFNMADD213SD xmm1, xmm2, xmm3/m64</p></td>
<td>RVM</td>
<td>V/V</td>
<td>FMA</td>
<td>Multiply scalar double-precision floating-point value from xmm1 and xmm2, negate the multiplication result and add to xmm3/mem and put result in xmm1.</td></tr>
<tr>
<td>
<p>VEX.DDS.LIG.66.0F38.W1 BD /r</p>
<p>VFNMADD231SD xmm1, xmm2, xmm3/m64</p></td>
<td>RVM</td>
<td>V/V</td>
<td>FMA</td>
<td>Multiply scalar double-precision floating-point value from xmm2 and xmm3/mem, negate the multiplication result and add to xmm1 and put result in xmm1.</td></tr>
<tr>
<td>
<p>EVEX.DDS.LIG.66.0F38.W1 9D /r</p>
<p>VFNMADD132SD xmm1 {k1}{z}, xmm2, xmm3/m64{er}</p></td>
<td>T1S</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Multiply scalar double-precision floating-point value from xmm1 and xmm3/m64, negate the multiplication result and add to xmm2 and put result in xmm1.</td></tr>
<tr>
<td>
<p>EVEX.DDS.LIG.66.0F38.W1 AD /r</p>
<p>VFNMADD213SD xmm1 {k1}{z}, xmm2, xmm3/m64{er}</p></td>
<td>T1S</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Multiply scalar double-precision floating-point value from xmm1 and xmm2, negate the multiplication result and add to xmm3/m64 and put result in xmm1.</td></tr>
<tr>
<td>
<p>EVEX.DDS.LIG.66.0F38.W1 BD /r</p>
<p>VFNMADD231SD xmm1 {k1}{z}, xmm2, xmm3/m64{er}</p></td>
<td>T1S</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Multiply scalar double-precision floating-point value from xmm2 and xmm3/m64, negate the multiplication result and add to xmm1 and put result in xmm1.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RVM</td>
<td>ModRM:reg (r, w)</td>
<td>VEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr>
<tr>
<td>T1S</td>
<td>ModRM:reg (r, w)</td>
<td>EVEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr></table>
<p><strong>Description</strong></p>
<p>VFNMADD132SD: Multiplies the low packed double-precision floating-point value from the first source operand to the low packed double-precision floating-point value in the third source operand, adds the negated infinite preci-sion intermediate result to the low packed double-precision floating-point values in the second source operand, performs rounding and stores the resulting packed double-precision floating-point value to the destination operand (first source operand).</p>
<p>VFNMADD213SD: Multiplies the low packed double-precision floating-point value from the second source operand to the low packed double-precision floating-point value in the first source operand, adds the negated infinite preci-sion intermediate result to the low packed double-precision floating-point value in the third source operand, performs rounding and stores the resulting packed double-precision floating-point value to the destination operand (first source operand).</p>
<p>VFNMADD231SD: Multiplies the low packed double-precision floating-point value from the second source to the low packed double-precision floating-point value in the third source operand, adds the negated infinite precision inter-mediate result to the low packed double-precision floating-point value in the first source operand, performs rounding and stores the resulting packed double-precision floating-point value to the destination operand (first source operand).</p>
<p>VEX.128 and EVEX encoded version: The destination operand (also first source operand) is encoded in reg_field. The second source operand is encoded in VEX.vvvv/EVEX.vvvv. The third source operand is encoded in rm_field. Bits 127:64 of the destination are unchanged. Bits MAXVL-1:128 of the destination register are zeroed.</p>
<p>EVEX encoded version: The low quadword element of the destination is updated according to the writemask.</p>
<p>Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction column.</p>
<p><strong>Operation</strong></p>
<p>In the operations below, “*” and “+” symbols represent multiplication and addition with infinite precision inputs and outputs (no rounding).</p>
<p><strong>VFNMADD132SD DEST, SRC2, SRC3 (EVEX encoded version)</strong></p>
<p>IF (EVEX.b = 1) and SRC3 *is a register*</p>
<p>THEN</p>
<p>SET_RM(EVEX.RC);</p>
<p>ELSE</p>
<p>SET_RM(MXCSR.RM);</p>
<p>FI;</p>
<p>IF k1[0] or *no writemask*</p>
<p>THEN</p>
<p>DEST[63:0] (cid:197) RoundFPControl(-(DEST[63:0]*SRC3[63:0]) + SRC2[63:0])</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[63:0] remains unchanged*</p>
<p>ELSE</p>
<p>; zeroing-masking</p>
<p>THEN DEST[63:0] (cid:197) 0</p>
<p>FI;</p>
<p>FI;</p>
<p>DEST[127:64] (cid:197) DEST[127:64]</p>
<p>DEST[MAX_VL-1:128] (cid:197) 0</p>
<p><strong>VFNMADD213SD DEST, SRC2, SRC3 (EVEX encoded version)</strong></p>
<p>IF (EVEX.b = 1) and SRC3 *is a register*</p>
<p>THEN</p>
<p>SET_RM(EVEX.RC);</p>
<p>ELSE</p>
<p>SET_RM(MXCSR.RM);</p>
<p>FI;</p>
<p>IF k1[0] or *no writemask*</p>
<p>THEN</p>
<p>DEST[63:0] (cid:197) RoundFPControl(-(SRC2[63:0]*DEST[63:0]) + SRC3[63:0])</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[63:0] remains unchanged*</p>
<p>ELSE</p>
<p>; zeroing-masking</p>
<p>THEN DEST[63:0] (cid:197) 0</p>
<p>FI;</p>
<p>FI;</p>
<p>DEST[127:64] (cid:197) DEST[127:64]</p>
<p>DEST[MAX_VL-1:128] (cid:197) 0</p>
<p><strong>VFNMADD231SD DEST, SRC2, SRC3 (EVEX encoded version)</strong></p>
<p>IF (EVEX.b = 1) and SRC3 *is a register*</p>
<p>THEN</p>
<p>SET_RM(EVEX.RC);</p>
<p>ELSE</p>
<p>SET_RM(MXCSR.RM);</p>
<p>FI;</p>
<p>IF k1[0] or *no writemask*</p>
<p>THEN</p>
<p>DEST[63:0] (cid:197) RoundFPControl(-(SRC2[63:0]*SRC3[63:0]) + DEST[63:0])</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[63:0] remains unchanged*</p>
<p>ELSE</p>
<p>; zeroing-masking</p>
<p>THEN DEST[63:0] (cid:197) 0</p>
<p>FI;</p>
<p>FI;</p>
<p>DEST[127:64] (cid:197) DEST[127:64]</p>
<p>DEST[MAX_VL-1:128] (cid:197) 0</p>
<p><strong>VFNMADD132SD DEST, SRC2, SRC3 (VEX encoded version)</strong></p>
<p>DEST[63:0] (cid:197)RoundFPControl_MXCSR(- (DEST[63:0]*SRC3[63:0]) + SRC2[63:0])</p>
<p>DEST[127:64] (cid:197)DEST[127:64]</p>
<p>DEST[MAX_VL-1:128] (cid:197)0</p>
<p><strong>VFNMADD213SD DEST, SRC2, SRC3 (VEX encoded version)</strong></p>
<p>DEST[63:0] (cid:197)RoundFPControl_MXCSR(- (SRC2[63:0]*DEST[63:0]) + SRC3[63:0])</p>
<p>DEST[127:64] (cid:197)DEST[127:64]</p>
<p>DEST[MAX_VL-1:128] (cid:197)0</p>
<p><strong>VFNMADD231SD DEST, SRC2, SRC3 (VEX encoded version)</strong></p>
<p>DEST[63:0] (cid:197)RoundFPControl_MXCSR(- (SRC2[63:0]*SRC3[63:0]) + DEST[63:0])</p>
<p>DEST[127:64] (cid:197)DEST[127:64]</p>
<p>DEST[MAX_VL-1:128] (cid:197)0</p>
<p><strong>Intel C/C++ Compiler Intrinsic Equivalent</strong></p>
<p>VFNMADDxxxSD __m128d _mm_fnmadd_round_sd(__m128d a, __m128d b, __m128d c, int r);</p>
<p>VFNMADDxxxSD __m128d _mm_mask_fnmadd_sd(__m128d a, __mmask8 k, __m128d b, __m128d c);</p>
<p>VFNMADDxxxSD __m128d _mm_maskz_fnmadd_sd(__mmask8 k, __m128d a, __m128d b, __m128d c);</p>
<p>VFNMADDxxxSD __m128d _mm_mask3_fnmadd_sd(__m128d a, __m128d b, __m128d c, __mmask8 k);</p>
<p>VFNMADDxxxSD __m128d _mm_mask_fnmadd_round_sd(__m128d a, __mmask8 k, __m128d b, __m128d c, int r);</p>
<p>VFNMADDxxxSD __m128d _mm_maskz_fnmadd_round_sd(__mmask8 k, __m128d a, __m128d b, __m128d c, int r);</p>
<p>VFNMADDxxxSD __m128d _mm_mask3_fnmadd_round_sd(__m128d a, __m128d b, __m128d c, __mmask8 k, int r);</p>
<p>VFNMADDxxxSD __m128d _mm_fnmadd_sd (__m128d a, __m128d b, __m128d c);</p>
<p><strong>SIMD Floating-Point Exceptions</strong></p>
<p>Overflow, Underflow, Invalid, Precision, Denormal</p>
<p><strong>Other Exceptions</strong></p>
<table>
<tr>
<td>VEX-encoded instructions, see Exceptions Type 3.</td></tr>
<tr>
<td>EVEX-encoded instructions, see Exceptions Type E3.</td></tr></table></body></html>